1. Field of the Invention
The invention relates to a memory apparatus and a test method, and in particular relates to an apparatus and a test method for a memory chip with reduced pin count circuit.
2. Description of the Related Art
With increased scope of memory chip and the complication of design thereof, test speed and accuracy of chips has become critical in determining efficiency of memory chip production. For example, design for testability (DFT) has been developed, in which enhanced circuit design during chip design stage efficiently reduces the time for chip tests, to improve failure coverage rate and product quality and production speed, as well as reducing the time for chip tests by a built-in self test (BIST).
A memory chip comprises a plurality of memory cells, some of which may be defective. Preparing faulty cells with redundant memory cells can address the problem. Defective memory cells are replaced with redundant memory cells by laser fuses. This stage is called as a fuse stage. The process to find the defective memory cells in a memory before the fuse stage is called a pre-fuse stage. After the fuse stage, the memory chip needs to be verified again. This process is called as a post-fuse stage.
Some memory chip test techniques check each memory cell in a memory chip during the pre-fuse stage, and then perform the fuse operation. Then an I/O compressor or a BIST determines whether the memory chip is recovered during the post-fuse stage. This techniques requires more time to find the defective memory cells in a chip during the pre-fuse stage, and testing apparatus requires more pin count to input the test data into the memory chip. Other memory chip test techniques find the defective memory cells in a memory chip during the pre-fuse stage and verify whether a defective memory cell exists during the post-fuse stage both by a BIST. This technique is less time-consuming and reduces pin count required but increases the manufacture cost of a chip by the high efficient (fast and correct verification) BIST which occupies more chip area and requires more complicated circuit design.